(1) Field of the Invention
The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and, more specifically, to methods of creating high performance electrical components (such as an inductor) on the surface of a semiconductor substrate by reducing the electromagnetic losses that are typically incurred in the surface of the substrate.
(2) Description of the Prior Art
The continued emphasis in the semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances of semiconductor processes and materials in combination with new and sophisticated device designs. Most of the semiconductor devices that are at this time being created are aimed at processing digital data. There are however also numerous semiconductor designs that are aimed at incorporating analog functions into devices that simultaneously process digital and analog data, or devices that can be used for the processing of only analog data. One of the major challenges in the creation of analog processing circuitry (using digital processing procedures and equipment) is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into devices that typically have feature sizes that approach the sub-micron range. The main components that offer a challenge in this respect are capacitors and inductors, since both these components are, for typical analog processing circuits, of considerable size.
A typical application for inductors of the invention is in the field of modern mobile communication applications that make use of compact, high-frequency equipment. Continued improvements in the performance characteristics of this equipment has over the years been achieved, further improvements will place continued emphasis on lowering the power consumption of the equipment, on reducing the size of the equipment, on increasing the operational frequency of the applications and on creating low noise levels. One of the main applications of semiconductor devices in the field of mobile communication is the creation of Radio Frequency (RF) amplifiers. RF amplifiers contain a number of standard components, a major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. Tuned circuits form, dependent on and determined by the values of their inductive and capacitive components, an impedance that is frequency dependent, enabling the tuned circuit to either present a high or a low impedance for signals of a certain frequency. The tuned circuit can therefore either reject or pass and further amplify components of an analog signal, based on the frequency of that component. The tuned circuit can in this manner be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at processing analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effects of parasitic capacitances that are part of a circuit. One of the problems that is encountered when creating an inductor on the surface of a semiconductor substrate is that the self-resonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies. As part of the design of such an inductor it is therefore of importance to reduce the capacitive coupling between the created inductor and the underlying substrate.
At high frequencies, the electromagnetic field that is generated by the inductor induces eddy currents in the underlying silicon substrate. Since the silicon substrate is a resistive conductor, the eddy currents will consume electromagnetic energy resulting in significant energy loss, resulting in a low Q capacitor. This is the main reason for a low Q value of a capacitor, whereby the resonant frequency of 1/√(LC) limits the upper boundary of the frequency. In addition, the eddy currents that are induced by the inductor will interfere with the performance of circuitry that is in close physical proximity to the capacitor.
It has already been pointed out that one of the key components that are used in creating high frequency analog semiconductor devices is the inductor that forms part of an LC resonance circuit. In view of the high device density that is typically encountered in semiconductor devices and the therefrom following intense use of the substrate surface area, the creation of the inductor must incorporate the minimization of the surface area that is required for the inductor, while at the same time maintaining a high Q value for the inductor. Typically, inductors that are created on the surface of a substrate are of a spiral shape whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC's) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing. It is clear that, by combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at the functions of analog data manipulation and analog data storage with the functions of digital data manipulation and digital data storage, a number of significant advantages can be achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions. The spiral form of the inductor that is created on the surface of a semiconductor substrate however results, due to the physical size of the inductor, in parasitic capacitances between the inductor wiring and the underlying substrate and causes electromagnetic energy losses in the underlying resistive silicon substrate. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application. More seriously, the inductor-generated electromagnetic field will induce eddy currents in the underlying resistive silicon substrate, causing a significant energy loss that results in low Q inductors.
The performance parameter of an inductor is typically indicated is the Quality (O) factor of the inductor. The quality factor Q of an inductor is defined as Q=Es/El, wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. For inductors that are created overlying a silicon substrate, the electromagnetic energy that is created by the inductor will primarily be lost in the resistive silicon of the underlying substrate and in the metal lines that are created to form the inductor. The quality factor for components differs from the quality that is associated with filters or resonators. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to the resistive silicon substrate, the resistance of the metal lines and dielectric losses. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit the upper bound of the cut-off frequency that can be achieved for the inductor using conventional silicon processes. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, such as for instance 50 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of a RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated, but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications, such as portable telephones and the like. Wireless communication is a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the value of the quality factor obtained from silicon-based inductors is significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have considerably lower substrate losses than their silicon counterparts (no eddy current, hence no loss of electromagnetic energy) and therefore provide much higher Q inductors. Furthermore, they have lower parasitic capacitance and therefore provide higher frequency operation capabilities. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed. It is known that GaAs is a semi-insulating material at high frequencies, reducing the electromagnetic losses that are incurred in the surface of the GaAs substrate, thereby increasing the Q value of the inductor created on the GaAs surface. GaAs RF chips however are expensive, a process that can avoid the use of GaAs RF chips therefore offers the benefit of cost advantage.
A number of different approaches have been used to incorporate inductors into a semiconductor environment without sacrificing device performance due to substrate losses. One of these approaches has been to selectively remove (by etching) the silicon underneath the inductor (using methods of micro machining), thereby removing substrate resistive energy losses and parasitic effects. Another method has been to use multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects.
Other approaches have used a high resistivity silicon substrate thereby reducing resistive losses in the silicon substrate. Resistive substrate losses in the surface of the underlying substrate form a dominant factor in determining the Q value of silicon inductors. Further, biased wells have been proposed underneath a spiral conductor, this again aimed at reducing inductive losses in the surface of the substrate. A more complex approach has been to create an active inductive component that simulates the electrical properties of an inductor as it is applied in active circuitry. This latter approach however results in high power consumption by the simulated inductor and in noise performance that is unacceptable for low power, high frequency applications. All of these approaches have as common objectives to enhance the quality (Q) value of the inductor and to reduce the surface area that is required for the creation of the inductor. The most important consideration in this respect is the electromagnetic energy losses due to the electromagnetic induced eddy currents in the silicon substrate.
When the dimensions of Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
Current techniques for building an inductor on the surface of a semiconductor substrate use fine-line techniques whereby the inductor is created under a layer of passivation. This however implies close physical proximity between the created inductor and the surface of the substrate over which the inductor has been created (typically less than 10 μm), resulting in high electromagnetic losses in the silicon substrate which in turn results in reducing the Q value of the inductor. By increasing the distance between the inductor and the semiconductor surface, the electromagnetic field in the silicon substrate will be reduced in reverse proportion to the distance, the Q value of the inductor can be increased. By therefore creating the inductor overlying the layer of passivation (by a post passivation process) and by, in addition, creating the inductor on the surface of a thick layer of dielectric (such as a polymer) that is deposited or adhered over the surface of a layer of passivation, the Q value of the inductor can be increased. In addition, by using wide and thick metal for the creation of the inductor, the parasitic resistance is reduced. The process of the invention applies these principles of post passivation inductor creation while the inductor is created on a thick layer of dielectric using thick and wide metals.
U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections.
U.S. Pat. No. 5,501,006 (Gehman, Jr. et a].,) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate.
U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention.
U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure.
U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers.
U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/0 traces.
U.S. Pat. No. 6,008,102 (Alford et al.) shows a helix inductor using two metal layers connected by vias.
U.S. Pat. No. 5,372,967 (Sundaram et al.) discloses a helix inductor.
U.S. 5'576,680 (Ling) and U.S. Pat. No. 5,884,990 (Burghartz et al.) show other helix inductor designs.